? 2011 microchip technology inc. ds80474b-page 1 pic24f04ka201 family the pic24f04ka201 family devices that you have received conform functionally to the current device data sheet (ds39937 b ), except for the anomalies described in this document. the silicon issues discussed in the following pages are for silicon revisions with the device and revision ids listed in ta bl e 1 . the silicon issues are summarized in table 2 . the errata described in this document will be addressed in future revisions of the pic24f04ka201 family silicon. data sheet clarifications and corrections start on page 5, following the discussion of silicon issues. the silicon revision level can be identified using the current version of mplab ? ide and microchip?s programmers, debuggers and emulation tools, which are available at the microchip corporate web site (www.microchip.com). for example, to identify the silicon revision level using mplab ide in conjunction with mplab icd 2 or pickit? 3: 1. using the appropriate interface, connect the device to the mplab icd 2 programmer/debugger or pickit? 3. 2. from the main menu in mplab ide, select c onfigure >s elect device and then select the target part number in the dialog box. 3. select the mplab hardware tool ( debugger >s elect tool ). 4. perform a ?connect? operation to the device ( debugger >c onnect ). depending on the devel- opment tool used, the part number and device revision id value appear in the output window. the devrev values for the various pic24f04ka201 family silicon revisions are shown in ta b l e 1 . note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated in the last column of table 2 apply to the current silicon revision ( a1 ). note: if you are unable to extract the silicon revision level, please contact your local microchip sales office for assistance. table 1: silicon devrev values part number device id (1) revision id for silicon revision (2) a1 pic24f04ka201 0b00h 01h PIC24F04KA200 0b02h note 1: the device ids (devid and devrev) are located at the last two implemented addresses in program memory. they are shown in hexadecimal in the format, ?devid devrev?. 2: refer to the ?pic24fxxkaxxx flash programming specification? (ds39919) for detailed information on device and revision ids for your specific device. pic24f04ka201 family silicon errata and data sheet clarification
pic24f04ka201 family ds80474b-page 2 ? 2011 microchip technology inc. table 2: silicon issue summary module feature item number issue summary affected revisions (1) a1 resets bor 1. inadvertent reset when disabling/enabling bor. x core deep sleep 2. failure to avoid deep sleep entry. x comparator ? 3. change in maximum v ioff .x spi enhanced buffer mode 4. errors when polling spitbf flag. x core low-voltage bor 5. lpbor configuration results in ambiguous resets. x comparator i/o pins 6. enabling comparators disables some digital i/o ports. x comparator ? 7. output polarity inversion also inverts edge-detect sensing. x core doze mode 8. instruction execution glitches following doze bit changes. x note 1: only those issues indicated in the last column apply to the current silicon revision.
? 2011 microchip technology inc. ds80474b-page 3 pic24f04ka201 family silicon errata issues 1. module: resets (bor) a device reset may occur if the bor is disabled and immediately re-enabled in software (rcon<14> is cleared, and then immediately set). work around it is recommended that several nop instructions be added to a bor disable/enable sequence. alternatively, place several instructions or a short routine between the instructions to disable and enable the bor. affected silicon revisions 2. module: core (deep sleep) deep sleep wake-up sources may be ignored if they occur just prior to entry into deep sleep mode. as a result, the device may enter deep sleep mode when it should not. work around if possible, configure external deep sleep wake-up sources to repeat themselves once. if the device does enter deep sleep, the second occurrence of the wake-up source will wake the device. alternatively, synchronize the entry into deep sleep with external wake-up sources, where possible. affected silicon revisions 3. module: comparator the maximum value for the input offset voltage (specification d300, v ioff ), shown in table 26-12 of the device data sheet, has changed for this silicon revision. the new value is shown in tab l e 3 (changes in bold ). work around none. affected silicon revisions table 3: comparator dc sp ecifications (partial) note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated by the shaded column in the following tables apply to the current silicon revision ( a1 ). a1 x a1 x a1 x param no. symbol characteristics min typ max units comments v ioff input offset voltage ? 20 60 mv
pic24f04ka201 family ds80474b-page 4 ? 2011 microchip technology inc. 4. module: spi (enhanced buffer mode) in enhanced buffer mode (spi1con2<0> = 1 ), polling the spi transmit buffer full bit, spitbf (spi1stat<1>), may produce erroneous results. this occurs only under two circumstances: ? in master mode, when the spi divide clock is 4 or greater. ? in slave mode, when the spi sample clock is slower than 1/4 of the cpu instruction time (t cy ). for master mode, this includes all combinations of the primary prescale bits (spi11con1<1:0>) and secondary prescale bits (spi1con1<4:2>) that, when combined, create an spi sample clock divisor with a value of four or greater. work around instead of polling the spitbf bit to test for an empty buffer (spi1stat<1> = 0 ), implement a spi receive interrupt handler in software and add to the spi transmit buffer in this routine. alternatively, poll the spi receive full bit, spirbf (spi1stat<0>), or the shift register empty bit, srmpt (spi1stat<7>), to determine when to service the spi transmit and transmit buffers. affected silicon revisions 5. module: core (low-power bor) when the low-power bor is enabled (fpor<6:5> = 00 ), brown-out reset events may result in a device reset in which both the bor and por bits are set. this differs from the expected behavior of simply re-arming the por circuit to ensure that a power-on reset occurs when v dd drops below the por threshold. work around none. affected silicon revisions 6. module: comparator (i/o pins) certain i/o pins may not function correctly as digital inputs or outputs after specific comparator outputs have been enabled with the coe bit (cmxcon<14> = 1 ). these are: ? rb14 (with comparator 1) ? ra6 (with comparator 2) this condition may continue, even after the com- parator in question has been disabled using the corresponding con bit (cmxcon<15> = 0 ). work around in addition to clearing the con bit, also clear the coe bit. affected silicon revisions 7. module: comparator when a comparator is programmed to trig- ger on certain edge-detect events (cmxcon<7:6> = 10 or 01 ), setting the cpol bit (cmxcon<13> = 1 ) may cause the comparator to flag the opposite edge-detect event (e.g., a high-to-low edge instead of the programmed low-to-high). work around leave cpol = 0 . in addition, use the opposite setting of cmxcon<7:6> to achieve the correct response (e.g., use ? 10 ? for ? 01 ?). affected silicon revisions a1 x a1 x a1 x a1 x
? 2011 microchip technology inc. ds80474b-page 5 pic24f04ka201 family 8. module: core (doze mode) operations that immediately follow any manipu- lations of the doze<2:0> or dozen bits (cldiv<14:11>) may not execute properly. in particular, for instructions that operate on an sfr, data may not be read properly. also, bits automatically cleared in hardware may not be cleared if the operation occurs during this interval. work around always insert a nop instruction before and after either of the following: ? enabling or disabling doze mode by setting or clearing the dozen bit ? before or after changing the doze<2:0> bits affected silicon revisions data sheet clarifications the following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (ds39937 b ): 1. module: electrical specifications (dc specifications) table 26-5 (?bor trip points?) has changed to reflect the functionality of the lpbor trip point (borv<1:0> = 00 ), and to make other typo- graphic corrections. the minimum and maximum values for the bor trip points in table 26-5 have changed. the new version of the table is shown below (changes in bold ). table 26-5: bor trip points a1 x note: corrections are shown in bold . where possible, the original bold text formatting has been removed for clarity. standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ max units conditions dc19 bor voltage on v dd transition bor v = 00 ? ? ? ? note (1) bor v = 01 2.92 3 3.25 v bor v = 10 2.63 2.7 2.92 v bor v = 11 1.75 1.82 2.01 v note 1: lpbor re-arms the por circuit, but does not cause a bor.
pic24f04ka201 family ds80474b-page 6 ? 2011 microchip technology inc. appendix a: document revision history rev a document (6/2009) initial release of this document; issued for revision a1. includes silicon issues 1 (resets ? bor), 2 (core ? deep sleep), 3 (comparator) and 4 (spi ? enhanced buffer mode). rev b document (2/2011) adds new silicon issues 5 (core ? low power bor), 6 and 7 (comparators), and 8 (core ? doze mode) to silicon revision a1. added data sheet clarification 1 (electrical specifications ? dc specifications) to revision b of the data sheet.
? 2011 microchip technology inc. ds80474b-page 7 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-893-1 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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